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This article shows you how to use Quartus timing simulation, the content is concise and easy to understand, can definitely brighten your eyes, through the detailed introduction of this article, I hope you can get something.

After completing the functional simulation, let's take a look at how the timing simulation works. Let's go back to the Quartus II software interface. In the Quartus II software interface, first of all, we need to fully compile our project. Then we open the Simulation/modelsim folder under the project, as shown in the figure.

On this page, we can see a lot of files, including the files generated by our functional simulation, as well as .vo files (Netlist files) and .sdo files (delay files). Only with these files can we carry out timing simulation. (if the .vo and .sdo files are not found, then you need to recreate the project, select ModelsimAltera,Verilog when selecting the EDA tool, and recompile the project after creation.) Then we can go back to the Quartus II software interface, and we find the [Tools] → [Run Simulation Tool] → [Gate Level Simulation] button in the menu bar and click it, as shown in the figure.

Here we can see that there are three modes, we can use the default, click [Run], and it will appear as shown in the picture. At this time, let's take a look at the LED1 and CLK_50M signals.

We can clearly see that they do not send changes at the same time, there is a delay between them. So far, we have completed the timing simulation. The above content is how to use Quartus timing simulation, have you learned the knowledge or skills? If you want to learn more skills or enrich your knowledge reserve, you are welcome to follow the industry information channel.

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