Shulou(Shulou.com)06/01 Report--

Editor to share with you the example analysis of the mixed structure of read priority and SRAM-MRAM, I believe that most people do not know much about it, so share this article for your reference. I hope you will learn a lot after reading this article. Let's learn about it together.

MRAM has the potential to replace SRAM and DRAM because of its many advantages. The MRAM memory constructed with the MTJ memory unit can be used as a cache. However, the long delay and high power consumption of MRAM write operations become its bottleneck, which hinders the further improvement of its performance. The two strategies of read priority write buffer and SRAM-MRAM hybrid structure can improve the performance of MRAM and reduce its power consumption.

Mixed structure of read first and SRAM-MRAM

Using MRAM directly instead of SRAM can lead to performance degradation. Therefore, two strategies are proposed to alleviate this contradiction: one is to introduce read-first write buffer, and the other is to introduce SRAM-MRAM hybrid structure. The two can be combined to improve the performance of the MRAM cache.

Read-first write buffer

Because the L2 cache fetches commands from the upper-level memory and the write buffer, there must be a priority strategy to resolve the conflict between read and write commands. For MRAM caching, the write latency is much greater than the read latency, so you should prevent write operations from blocking read operations.

Two rules are proposed to ensure the priority of read operations:

(1) read operations always have priority over write operations.

(2) when the write operation blocks the read operation and the write buffer is not full, the read command can abort the current write operation if certain priority conditions are met. Then read the command to get the execution power. The aborted write operation is retried later. The completion degree α is used as the priority condition, and the read command will not get priority when the completion degree is lower than α. After simulation, α is determined to be 50%, which can meet various working conditions. Implementing this strategy requires a counter, counting from O when writing begins. The cache controller checks the counter and then decides whether to abort the current write operation to perform the read operation. This strategy eliminates the performance degradation compared to the direct replacement of SRAM with MRAM, but consumes more power because some writes need to be reperformed.

L2 cache with SRAM-MRAM hybrid structure

The researchers propose to replace pure MRAM memory with SRAM-MRAM hybrid structure, of which SRAM accounts for only a small part. Its main purpose is to concentrate write operations on SRAM as much as possible and reduce the number of write operations in MRAM.

Figure 1SRAM-MRAM mixed structure

As shown in figure 1, the researchers reduced part of the MRAM and replaced it with sram, and grouped all the SRAM units together to build several complete SRAM groups on the processor layer. The SRAM group is placed in the center of the processor layer rather than scattered, so that the area of the processor layer increases and the area of the cache layer decreases.

Several management strategies of mixed structure are given.

(1) the cache controller needs to know the location of SRAM and MRAM. When a write error occurs, the controller gives priority to putting the data into the SRAM.

(2) considering the possibility that the processor repeatedly writes data to some units, if the data is in MRAM, it needs to be moved into SRAM. If the data goes through two consecutive write operations, the data needs to be moved into the SRAM.

(3) notice that the read operation of the processor may also cause the transfer of data, and the number of times may be greater than the write operation. Therefore, a new data movement strategy is introduced. For the traditional management strategy, the data is moved to the host group, while the strategy adapted to the hybrid structure moves the data into the SRAM.

(4) the results show that the average performance of the hybrid structure is improved by 5.65%, and the average total power consumption is reduced by 12.45%.

The above is all the content of the article "sample Analysis of read priority and SRAM-MRAM mixed structure". Thank you for reading! I believe we all have a certain understanding, hope to share the content to help you, if you want to learn more knowledge, welcome to follow the industry information channel!

Welcome to subscribe "Shulou Technology Information " to get latest news, interesting things and hot topics in the IT industry, and controls the hottest and latest Internet news, technology news and IT industry trends.