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What this article shares with you is about the composition, working principle and development process of FPGA. The editor thinks it is very practical, so I share it with you to learn. I hope you can get something after reading this article.

1. Overview of FPGA

FPGA is the abbreviation of English Field Programmable Gate Array, that is, field programmable gate array. It is the product of further development on the basis of programmable devices such as PAL, GAL, EPLD and so on. It appears as a kind of semi-custom circuit in the field of application specific integrated circuit (ASIC). It not only solves the deficiency of custom circuit, but also overcomes the disadvantage of limited number of gate circuits of original programmable devices.

2. FPGA chip structure

The FPGA chip is mainly composed of three parts, namely IOE (input output element, input and output unit), LAB (logic array block, logic array block, which is called CLB for Xilinx) and Interconnect (internal connection line).

2.1 IOE

IOE is the physical interface between the chip and the external circuit, which mainly completes the driving and matching requirements of input / output signals under different electrical characteristics, such as from basic LVTTL/LVCMOS interface to PCI/LVDS/RSDS and even various differential interfaces, and from 5V compatibility to 3.3V/2.5V/1.8V/1.5V level interface. The following is the IOE structure of ALTERA's Cyclone IV EP4CE115F29 equipment.

IOE structure diagram of EP4CE115F29 equipment

FPGA's IOE is classified by group, and each group can independently support different IO standards. Through the flexible configuration of the software, it can match different electrical standards and IO physical characteristics, and can adjust the drive current and change the up / down resistors. Cyclone IV devices have 8 IO blank (groups), as shown in the following figure:

LAB structure diagram

LE is the smallest logic unit of a Cyclone IV device. Each LE is mainly composed of LUT and registers.

Implementation schematic diagram of LUT

2.3 Interconnect

FPGA is rich in internal connections, mainly Row interconnect, column interconnect, Direct link interconnect, and Local interconnect and Register chain interconnect (connection lines between registers) in figure 3, as described in the data manual.

The internal connection cable connects all the units within the FPGA, and the length and process of the connection determine the driving capacity and transmission speed of the signal reconnection line. In the actual development, the designer does not need to select the connection line directly, and the layout router can automatically select the connection line to connect each logic unit according to the topological structure and constraints of the input logic Netlist (which is generated by synthesis). In essence, the use of wiring resources is closely and directly related to the results of the design.

3. How FPGA works

FPGA uses a small look-up table (16 × 1RAM) to implement combinational logic. Each lookup table is connected to the input of a D flip-flop (see figure 4), and the flip-flop drives other logic circuits or drives Imax O, thus forming a basic logic unit module that can realize both combinational logic function and sequential logic function. These modules are connected with each other or connected to Icano module by metal connection. The logic of FPGA is realized by loading programming data into the internal static storage unit. The value stored in the memory cell determines the logic function of the logic unit and the connection mode between each module or between the module and the FPGA O, and finally determines the function that FPGA can achieve. FPGA allows unlimited programming.

4. FPGA development process

Schematic diagram and HDL (Hardware description language, hardware description language) are the two most commonly used digital hardware circuit description methods. Among them, HDL design method has the characteristics of better portability, versatility, module division and reusability, so it is widely used in current engineering design. The following development process when familiar with FPGA design is based on HDL.

The development process of FPGA

1) system function design

Before the system design, the first thing is to carry out the preparatory work such as scheme demonstration, system design and FPGA chip selection. According to the task requirements, such as the index and complexity of the system, the system engineer weighs the working speed and various resources and costs of the chip itself, and chooses a reasonable design scheme and appropriate device types. Generally, the top-down design method is used to divide the system into several basic units, and then each basic unit is divided into the next basic unit, which is done until the EDA component library can be used directly.

2) RTL-level HDL design

RTL level (Register Transfer Level, register transfer level) refers to the HDL design method of a model that does not pay attention to the details of registers and combinational logic (such as how many logic gates are used, the connection topology of logic gates, etc.), by describing the flow of data between registers and how to deal with and control these data flows. The RTL level is more abstract, simpler and more efficient than the door level. The most important feature of RTL level is that it can be synthesized into gate-level Netlist directly with synthesis tools, in which RTL level design directly determines the function and efficiency of the system.

3) RTL level simulation

Also known as function (behavior) simulation, or pre-synthesis simulation, is to verify the logic function of the circuit designed by the user before compilation. At this time, the simulation has no delay information and only detects the preliminary function. Before simulation, waveform files and test vectors should be established by using waveform editor and HDL (that is, the concerned input signals are combined into sequences). The simulation results will generate report files and output signal waveforms, from which the changes of each node signal can be observed. If an error is found, return to the design to modify the logical design. The commonly used tools are ModelSim of Model Tech, VCS of Sysnopsys, NC-Verilog of Cadence and NC-VHDL. Although functional simulation is not a necessary step in the process of FPGA development, it is the most critical step in system design.

In order to improve the efficiency of functional simulation, it is necessary to establish a test platform testbench, whose test incentives are generally described by behavioral HDL language, in which RTL-level modules are synthesizable, which is a subset of behavior-level modules.

4) Synthesis

The so-called synthesis is to transform the description of the higher level of abstraction into the description of the lower level. The logical connection generated by comprehensive optimization is optimized according to the goals and requirements, so that the hierarchical design is flattened, which can be realized by FPGA layout and routing software. According to the current level, comprehensive optimization (Synthesis) refers to compiling the design input into a logical connection Netlist composed of basic logic units such as gate, OR gate, non-gate, RAM, flip-flop and so on, rather than a real gate-level circuit. The real and specific gate-level circuits need to be generated according to the standard gate-level structure Netlist generated by the synthesis using the layout and routing function of the FPGA manufacturer. In order to convert to a standard gate-level structure Netlist, the HDL program must be written in accordance with the style required by a particular synthesizer. Because the synthesis of gate-level structure and RTL-level HDL programs is a very mature technology, all synthesizers can support this level of synthesis. The commonly used comprehensive tools are the Synplify/Synplify Pro software of Synplicity Company and the comprehensive development tools launched by various FPGA manufacturers.

5) Gate-level simulation

Also known as post-synthesis simulation, post-synthesis simulation checks whether the synthesis results are consistent with the original design. In the simulation, the standard delay file generated by the synthesis is inversely tagged into the comprehensive simulation model, and the impact of gate delay can be estimated. However, this step can not estimate the line delay, so there is still a certain gap between this step and the actual situation after wiring, which is not very accurate. The current synthesis tools are more mature, and this step can be omitted for general design, but if the circuit structure is found to be inconsistent with the design intention after layout and routing, it is necessary to go back to the post-synthesis simulation to confirm the problem. The software tools introduced in functional simulation generally support integrated post-simulation.

6) layout and routing

The realization is to configure the logic Netlist generated by synthesis to a specific FPGA chip to match the logic and timing of the project with the available resources of the device. Layout and routing is one of the most important processes. The layout reasonably configures the hardware primitives and underlying units in the logical Netlist to the inherent hardware structure inside the chip, and often needs to make a choice between the optimal speed and the optimal area. According to the topological structure of the layout, the wiring uses all kinds of connection resources inside the chip to connect each component reasonably and correctly. Layout and routing can also be simply understood as the reasonable allocation of FPGA internal lookup table and register resources, the layout can be understood to select the optimal combination of resources that can realize the design of Netlist, and routing is to connect these lookup tables and register resources in an optimal way.

At present, the structure of FPGA is very complex, especially when there are timing constraints, we need to use timing-driven engine for placement and routing. After cabling, the software tool automatically generates a report on the use of resources in each part of the design. Since only the FPGA chip manufacturer knows the chip structure best, the placement and routing must choose the tools provided by the chip developer.

7) timing simulation

It refers to reverse tagging the delay information of layout and routing to the design Netlist to detect whether there is a timing violation (that is, it does not meet the timing constraints or the inherent timing rules of the device, such as setup time, hold time, etc.). Timing simulation contains the most complete and accurate delay information, which can better reflect the actual working situation of the chip. Because the internal delay of different chips is different, different layout and routing schemes also have different effects on the delay. Therefore, after the layout and routing, through the timing simulation of the system and each module, it is very necessary to analyze the timing relationship, estimate the system performance, and check and eliminate competitive risks.

8) FPGA board level debugging

Through the programmer, the configuration file after layout and wiring is downloaded to FPGA, and its hardware is programmed. Configuration files are generally in .pof or .sof file format, and download methods include AS (active), PS (passive), JTAG (boundary scan) and so on.

Logic Analyzer (Logic Analyzer,LA) is the main debugging tool for FPGA design, but it needs to draw out a large number of test pins, and LA is expensive. At present, the mainstream FPGA chip manufacturers provide embedded on-line logic analyzers (such as ChipScope in Xilinx ISE, SignalTapII in Altera QuartusII and SignalProb) to solve the above contradictions. They only need to occupy a small amount of logic resources of the chip and have high practical value.

The above is the composition, working principle and development process of FPGA. The editor believes that there are some knowledge points that we may see or use in our daily work. I hope you can learn more from this article. For more details, please follow the industry information channel.

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