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2025-01-29 Update From: SLTechnology News&Howtos shulou NAV: SLTechnology News&Howtos > Servers >
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This article mainly explains "what is the paging mechanism of Linux system memory addressing". The content of the article is simple and clear, and it is easy to learn and understand. Please follow the editor's train of thought to study and learn "what is the paging mechanism of Linux system memory addressing"?
The paging mechanism is carried out after the segment mechanism to complete the linear-physical address translation process. The segment mechanism converts the logical address into a linear address, and the paging mechanism further converts the linear address into a physical address.
Paging in hardware
The paging mechanism is enabled by the PG bit in CR0. For example, PG=1, enable the paging mechanism and use the mechanism described in this section to convert linear addresses into physical addresses. For example, PG=0 disables the paging mechanism and directly uses the linear address generated by the segment mechanism as a physical address. The paging mechanism manages objects that are fixed-size blocks of storage, called pages (page). The paging mechanism regards the whole linear address space and the whole physical address space as composed of pages, and any page in the linear address space can be mapped to any page in the physical address space (we call a page or page frame (page frame) in the physical space).
80386 pages that use 4K bytes. Each page has 4K bytes long and is aligned on the boundary of 4K bytes, that is, the starting address of each page is divisible by 4K. As a result, 80386 divides the linear address space of 4G bytes into 1G pages, each with a 4K byte size. The paging mechanism manages the pages in the linear address space by relocating them to the physical address space, because the entire 4K bytes of each page are mapped as a unit, and each page aligns the boundaries of 4K bytes, so the lower 12 bits of the linear address are directly used as the lower 12 bits of the physical address by the paging mechanism.
Why use two-level page tables
Assuming that each process occupies 4G linear address space, the page table contains 1m table items, each accounting for 4 bytes, then the page table of each process occupies 4m memory space. In order to save the space occupied by the page table, we use two-level page table. Each process is assigned a page directory, but only when the page table is actually used will it be allocated to memory. The first-level page table needs to allocate all the page table space at once, while the two-level page table can allocate the page table space when needed.
Two-level page table structure
The first level of the two-level table structure is called the page directory and is stored in a 4K-byte page. The page catalog table has 1K table items, each with 4 bytes, and points to the second-level table. The highest 10 bits of the linear address (bit 31 ~ bit 32) are used to generate the first-level index. one of the 1K second-level tables is specified and selected from the table items obtained by the index.
The second level of the two-level table structure is called the page table, which also happens to be stored in a 4K-byte page with 1K-byte table items, each containing the physical base address of a page. The second-level page table is indexed by the middle 10 bits of the linear address (bit 21 ~ bit 12) to obtain the page table entry containing the physical address of the page. the high 20 bits of this physical address and the lower 12 bits of the linear address form the final physical address. that is, the physical address output by the page conversion process.
Page catalog entry
Bits 31-12 are 20-bit page table addresses. Since the lower 12 bits of the page table address are always 0, it is OK to indicate the 32-bit page table address with the higher 20 bits. Therefore, a page directory contains a maximum of 1024 page table addresses.
Bit 0 is the existing bit. If page1 indicates that the page pointed to by the page table address is in memory, if paired 0 means that it is not in memory.
The first bit is the read / write bit, and the second bit is the user / administrator bit, which provide hardware protection for page directory entries. When a process with privilege level 3 wants to access the page, it needs to pass the page protection check, while the process with privilege level 0 can bypass page protection.
The third bit is the PWT (Page Write-Through) bit, which indicates whether to use write-through mode, which means both write-through memory (RAM) and write cache. A bit of 1 indicates that write-through mode is used.
The fourth bit is the PCD (Page Cache Disable) bit, which indicates whether caching is enabled, and a bit of 1 means caching is enabled.
The fifth bit is the access bit, and when accessing the page catalog item, the A bit = 1.
Bit 7 is the Page Size flag, which applies only to page catalog entries. If set to 1, the page catalog entry refers to the 4MB page, see the extended paging below.
Bits 9-11 are dedicated to the operating system, and Linux does not do anything special.
Page item
Each page catalog entry in 80386 points to a page table, which contains up to 1024 page items of 4 bytes each, including the starting address of the page and information about the page. The starting address of the page is also an integral multiple of 4K, so the lower 12 bits of the page are also reserved for other purposes.
Bits 31-12 are 20-bit physical page addresses. Bits 0-5 and 911 except bit 6 are used for the same purpose as the page entry, and bit 6 is unique to the page item. When the page involved is written, the D bit is set to 1.
4GB's memory has only one page directory, it has a maximum of 1024 page entries, and each page directory entry contains 1024 page entries, so the memory can be divided into 1024 × 10241m pages. Since each page is 4K bytes, the memory size is exactly 4GB at most.
Translation from linear address to physical address
32-bit linear address to physical address translation
1.CR3 contains the starting address of the page directory, uses the highest 10-bit A31~A22 of the 32-bit linear address as the index of the page directory entry, multiplies it by 4, and adds it with the starting address of the page directory in CR3 to form the address of the corresponding page table.
two。 Retrieves a 32-bit page entry from the specified address with a lower 12-bit 0, which is the starting address of the page table. The A21~A12 bit in the 32-bit linear address is used as the index of the page in the page table, multiplied by 4, and added to the starting address of the page table to form a 32-bit page address.
3. A11~A0 is added to the 32-bit page address as an offset from the page address to form a 32-bit physical address.
Extended paging
Starting with the Pentium processor, the Intel microprocessor introduced extended paging, which allows pages to be 4MB in size.
In the case of extended paging, the paging mechanism divides the 32-bit linear address into two fields: a directory domain of up to 10 bits and an offset of the remaining 22 bits.
Page cache
Because in the case of paging, each memory access has to access the two-level page table, which greatly reduces the access speed. Therefore, in order to improve speed, a caching hardware mechanism for recently accessed pages is set in 386, which automatically maintains 32 recent page addresses used by the processor, so that 128K bytes of memory addresses can be overwritten. When accessing the memory, first check whether the page to be accessed is in the cache, if so, you do not have to go through two levels of access, if not, then two levels of access. On average, the page cache has a hit rate of about 98%, which means that only 2% of cases have to access a two-tier paging mechanism every time memory is accessed. This greatly speeds up the speed.
Paging Mechanism in Linux
Linux uses a paging mechanism suitable for 32-bit and 64-bit systems.
Page global catalog
Page top-level directory
Middle page directory
Page table
The page global catalog contains the addresses of several page parent directories, which in turn contains the addresses of several page middle directories, which in turn contain the addresses of several page tables. Each page table item points to a page frame. The linear address is therefore divided into five parts. The number of bits is not shown in the figure because the size of each part is related to the specific computer architecture.
For 32-bit systems that do not have physical address extension enabled, two-level page tables are sufficient. In essence, Linux completely cancels the page parent directory and page middle directory fields by making the "page parent directory" and "page middle directory" bits all 0. However, the position of the page parent directory and the page middle directory in the pointer sequence is retained so that the same code can be used on both 32-bit and 64-bit systems. The kernel reserves a location for the page parent directory and the page middle directory by setting the number of page directory entries to 1 and mapping these two directory entries to an appropriate directory entry in the page global catalog.
A 32-bit system with physical address extension enabled uses a three-level page table. The page global catalog of Linux corresponds to the 80 × 86 page catalog pointer table (PDPT), canceling the page parent catalog, the page middle directory corresponds to the 80 × 86 page directory, and the Linux page table corresponds to the 80 × 86 page table.
Finally, whether a 64-bit system uses level 3 or level 4 paging depends on how the hardware divides the bits of the linear address.
Thank you for reading, the above is the content of "what is the paging mechanism of memory addressing in Linux system". After the study of this article, I believe you have a deeper understanding of what the paging mechanism of memory addressing in Linux system is, and the specific use needs to be verified in practice. Here is, the editor will push for you more related knowledge points of the article, welcome to follow!
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